SFR+100 and R+100 8065 memory access

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wwhite
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Re: SFR+100 and R+100 8065 memory access

Unread post by wwhite »

This has been a fun distraction from every day life.
For me, I have learned a lot more about differences with 8061 and 8065, specifically with how the uP decodes how to select different banks.

Once this covid stuff is settled, I would like to buy you jsa, a beer, or a pop whatever you prefer(seriously)!.

SFRs do not use +100, only general registers if there are more than one 64k byte memory chips on board and some other circuit details.

The hardware does what we expect. Its the disassembly process that is incorrect.
The disassembly does not know how many fixed hardware 64k memory banks exists in box.

The software nor the hardware cares if you try and access a word with ODD addressing, it works.
With one 64K bank memory(bank 0, or #8 as default, still one bank), lets use R3b again, uP will access register 0x3a.
With two or more 64K bank memory, Direct word addressing will access the odd bank pair bit A0, with the pair being select from PSW 9.

If PSW bit 9 is 0, that would select the bank pair 0 or 1. address bit A0 is odd, so it would select bank 1 register 0x3a.
Bank 1 0x3a, otherwise known as your +100, will show in disassembly as register 0x13a

Again, if your hardware only has bank0, the register will be accessed as +000, register 0x03a.

Your test code shows that single bank hardware, access to word registers 0x3b and 0x13a are different(single bank)
Your test code shows that in multi bank hardware, access to word registers 0x3b and 0x13a are the same(3b odd, bank1, 0x13a bank 1 0x3a).

Does that clear it up?
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Re: SFR+100 and R+100 8065 memory access

Unread post by jsa »

wwhite wrote: 16 Apr 2021, 12:07 This has been a fun distraction from every day life.
For me, I have learned a lot more about differences with 8061 and 8065, specifically with how the uP decodes how to select different banks.

Once this covid stuff is settled, I would like to buy you jsa, a beer, or a pop whatever you prefer(seriously)!.
Cool. I'm on an island in the south pacific, drop by some time. :)
wwhite wrote: 16 Apr 2021, 12:07SFRs do not use +100, only general registers if there are more than one 64k byte memory chips on board and some other circuit details.
Look at the results for the second test bin. Address x102 to x123 can be accessed using word operations on odd SFR addresses.

Testing one off single ROM bank uP is not enough to be certain of every single ROM back hardware config. They still have R0 to R3FF onboard the uP.
wwhite wrote: 16 Apr 2021, 12:07The hardware does what we expect.
I disagree.
wwhite wrote: 16 Apr 2021, 12:07Its the disassembly process that is incorrect.
Agree it is a work in progress.
wwhite wrote: 16 Apr 2021, 12:07 The disassembly does not know how many fixed hardware 64k memory banks exists in box.
Disagree, printout at the top of the LST file says how many ROM banks are found.
jsa
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Re: SFR+100 and R+100 8065 memory access

Unread post by jsa »

wwhite wrote: 16 Apr 2021, 04:24
You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.
Noted.
Non-memory expansion mode set in software only? What is the voltage on PIN-27 of the CPU? (+5v or gnd)
I'm sure the uP are the same, its the circuit board and components are different.
Pin 27 does not matter to memory, it is for I/O expansion. Input and Output...Sensors and Actuators.

wwhite wrote: 16 Apr 2021, 04:24 I claim "Single 64k memory bank hardware will not support sf/r+100, plain and simple, whether it be a 8061 or an 8065".
Hardware being the circuit board, peripherals, etc. not the uP.
Or one could say; "It Depends", the 8065 can be configured to support it, and it can also be configured to not support it.
The relevance, to +100 addressing, of hardware external to the uP has not been established.
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