Lets look at what the Sub2340_test is doing, in detail, and we'll use PSW bit 9 and bit 8 set/clear for the fun of it.
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2340: a1,64,00,3c ldw R3c,64 Odd_Md_Val = 64; # Load test value for Direct Odd Mode Addressing
Pretty straight forward, ^A1 opcode is LDW Immediate addressing mode.
PSW bit 9 = 0, select bank Bank0 or Bank1
Data word is even, destination breg is even, select least significant bank or even bank(Bank0 or Bank2),
Register 3c will be located in Bank0.
What happens when PSW bit 9 is set?
PSW bit 9 = 1, select bank Bank2 or Bank3
Data word is even, destination breg is even, select least significant bank or even bank(Bank0 or Bank2),
Register 3c will be located in Bank2
Next line of code:
RAM bank selection for an 8-bit address pointer reference relies solely upon the logic state of PSW bits 8 and 9.
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2344: c7,01,3a,01,3c stb R3c,[R0+13a] Odd_Md_Rg = Odd_Md_Val;
^C7 opcode is STB Long Indexed addressing.
PSW bit 9 = 0, select bank Bank0 or Bank1
PSW bit 8 = 0, select Bank0
IndexRa = R0, offset = 13a, breg = R3c, [Ra] = R13a(000)
Bank0 ^3c -> (^13a + (Bank0 + R^00))
Bank0 ^3c -> (Bank1 + 3a)
Destination Register R3c in Bank0 will contain the value from Register R3a in Bank1.
What happens when PSW bit 9 = 1, and bit 8 =1?
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PSW bit 9 = 1, select bank Bank2 or Bank3
PSW bit 8 = 1, select Bank3
IndexRa = R0, offset = 13a, breg = R3c, [Ra] = R13a(300)
Bank3 ^3c -> (^13a + (Bank3 + R^00))
Bank3 ^3c -> ( Bank1 + 3a)
Destination Register R3c in Bank3 will contain the value from Register R3a in Bank1.
Next line of code, similar to previous, but with an ODD offset:
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2349: c7,01,3b,01,3d stb R3d,[R0+13b] Odd_Md_Rg^ = Odd_Md_Val;
Odd offsets have no effect on Indirect or Indexed, only PSW bit 8 and 9 have complete control of what bank of Byte operation registers to use.
Next line of code:
(side note: this is a fun exercise, I'm learning so much
)
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234e: a1,3a,3b,3a ldw R3a,3b3a Even_Md_Rg = 3b3a;
^A1, LDW Immediate addressing
Data = 0x3b3a, Destination = R3a
PSW bit 9 = 0, select bank Bank0 or Bank1
Destination breg is even, select least significant bank or even bank(Bank0 or Bank2),
Register 3a will be located in Bank0.
What happens when PSW bit 9 is set?
PSW bit 9 = 1, select bank Bank2 or Bank3
Destination breg is even, select least significant bank or even bank(Bank0 or Bank2),
Register 3a will be located in Bank2
Almost there, to see results....
Next line of code, ODD addressing
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2352: a0,3b,30 ldw R30,R13a Log_Rg = Odd_Md_Rg;
^A0 LDW Direct word addressing
PSW bit 9 = 0, select bank Bank0 or Bank1
SourceRA R3b is ODD, we select Bank1 (areg = address bits 1-7 = R3a)
DestRB = R30, is EVEN, we select Bank0
Register R30 in Bank0 is loaded with the value from Register R3a in Bank1.
What happens if PSW bit 9 =1?
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2352: a0,3b,30 ldw R30,R13a Log_Rg = Odd_Md_Rg;
^A0 LDW Direct word addressing
PSW bit 9 = 1, select bank Bank2 or Bank3
SourceRA R3b is ODD, we select Bank3 (areg = address bits 1-7 = R3a)
DestRB = R30, is EVEN, we select Bank2
Register R30 in Bank2 is loaded with the value from Register R3a in Bank3.
Last line of code, I promise:
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2355: c3,01,10,04,30 stw R30,[R0+410] Mode_Result = Log_Rg;
^C3, STW, Long Indexed
// don't care about PSW
// also don't care about EVEN or ODD address spaces
// now we are only concerned with Address bits 8 an 9, to select RAM Bank#.
IndexRA = R0, offset = 410, breg = R30, [Ra] = R30(000)
A8, A9 = 0x0410 = 0B0000 0100 0000 1010, bit 8=0, bit9=0, select Bank0
Bank0 ^30 -> (^410 + (Bank0 + R^00))
Bank0 ^30 -> Bank0 + 410
Register R410 will have value of R30 both in Bank0
Lets do a summary table:
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Register. |. Symbol. |. Bank#. | Value
R3a. |. Even_Md_Rg. | Bank0 if PSW9=0. | 3b3a
| Bank2 if PSW9=1 |
R3c. |. Odd_Md_Val. |Bank0 if PSW9=0. | 64
| Bank2 if PSW9=1 |
R3c. | byte_low.(13a) | Depends on PSW(8,9)
| Bank0 (0,0) | 3a
| Bank1 (1,0) | ?indeterminate?
| Bank2 (0,1) | 3a
| Bank3 (1,1) | ?indeterminate?
R3d. |. byte_hi. | | Depends on PSW(8,9)
| Bank0 (0,0) | 3b
| Bank1 (1,0) | ?indeterminate?
| Bank2 (0,1) | 3b
| Bank3 (1,1) | ?indeterminate?
R13a. | |. |
R13b. |
R30. |. Log_Rg. (ODD). | Bank0 if PSW9=0.|R3a from Bank1
| Bank2 if PSW9=1 | R3a from Bank3
R410 |. Mode_Result. | Bank0 | value from R30 in Bank0
So, as you can see, the only Data Banks being used are 0 and 2, with the original 3b3a and 64 word values.
Reg R30, with ODD addressing loads values from Bank1 and Bank3, which have not been initialized.
I really do not see, or understand how your test cases are valid.