EFIDynoTuning Forum

Here is proof it is an EEC-IV 8061:

wwhite wrote: ↑2021 Apr 15, 17:14
Back to your test code: a0,3b,30 ldw R30,R13a Log_Rg = Odd_Md_Rg;
Two possible results:
- 1) R30 could contain R13a=0x0064 (d100)
- 2) R30 could contain R3b=0x3b3a. (d15162)

Yes, now you see it.
STB put 0x0064 at address R13A.

R3a,R3b Endian unadjusted has 0x3a,0x3b.
Endian adjusted the value is 0x3b3a.
No word R3b.

wwhite wrote: ↑2021 Apr 15, 18:15 Here is proof it is an EEC-IV 8061:
Screen Shot 2021-04-15 at 3.12.26 PM.png

No its not proof.

8065's in boxes labelled as eec-iv are like weeds.

Suck the code out of it, it is 8065 code.

Pull the lid off it, it is an 8065 inside with 8065 support chip.

U gonna hafta do betta than google pic search

I don't refer to eec-i/v, I say 8061 or 8065 these days.

wwhite wrote: ↑2021 Apr 15, 17:42 I am assuming it is the following test results d100 and d15162 that show up on different uPs.

Run the test bins, no need to assume.

wwhite wrote: ↑2021 Apr 15, 17:42 Simple with your test cases, P3M is a 8061,

No, it is 8065.

wwhite wrote: ↑2021 Apr 15, 17:42 With P3M being 8061 and VILE being 8065, you have not proved that this does not work on a 8065.

P3M hardware is 8065 and the test result show that sf/r+100 did not work on that hardware.

VILE hardware is 8065 and the test result show that sf/r+100 did work on that hardware.

wwhite wrote: ↑2021 Apr 15, 18:13

jsa wrote: ↑2021 Apr 15, 18:09 No, P3M is not 8061, it is 8065.

Prove it.

Did you see the stack setting in the test bins...

Try running those test bins.

'P3M' (8065, single bank)

Ok, so, the answer is going to be any single bank uP does not support SFR+100 or R+100, where as multi banks do support.

wwhite wrote: ↑2021 Apr 15, 19:19 'P3M' (8065, single bank)

Ok, so, the answer is going to be any single bank uP does not support SFR+100 or R+100, where as multi banks do support.

Which particular memory bank type are you talking about?

jsa wrote: ↑2021 Apr 15, 19:28 Which particular memory bank type are you talking about?

Both RAM and ROM.
The P3M.bin is a single bank, and your hardware box does not support bank addressing.

Without having the hardware in hand, I would have to assume that the circuit board does not have the addressing chip that supports bank addressing or it simply does not have the external memory that supports multi bank.

Can you identify which memory chips that are on your hardware?

wwhite wrote: ↑2021 Apr 15, 23:01 Both RAM and ROM...

0x0 to 0x3ff resides within the uP, not external circuits.

Sf/r+100 is happening inside the uP, not external circuits.

You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.

It is premature to boldly claim that single ROMBANK do not support sf/r+100.

jsa wrote: ↑2021 Apr 15, 23:43 0x0 to 0x3ff resides within the uP, not external circuits.

Correct, memory mapped for speed. SFR 0x00->0x23, Gen. Reg. 0x24->0x3ff for the 8065.
0x0400->0xffff ~57k, one bank is ~64k

Sf/r+100 is happening inside the uP, not external circuits.

Oh boy, here we go with this +100 business. There is no +100 inside the uP, thats a human thing.
Inside the uP there is an algorithm that selects which bank pair, either odd or even, using PSW bits and address bits.

You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.

Noted.
Non-memory expansion mode set in software only? What is the voltage on PIN-27 of the CPU? (+5v or gnd)
I'm sure the uP are the same, its the circuit board and components are different.

It is premature to boldly claim that single ROMBANK do not support sf/r+100.

I noted the P3M.bin is a single bank, and "your hardware box does not support bank addressing."

I claim "Single 64k memory bank hardware will not support sf/r+100, plain and simple, whether it be a 8061 or an 8065".
Hardware being the circuit board, peripherals, etc. not the uP.
Or one could say; "It Depends", the 8065 can be configured to support it, and it can also be configured to not support it.