SFR+100 and R+100 8065 memory access
-
- Posts: 320
- Joined: 2021 Feb 16, 15:53
- Location: Victoria, BC, Canada
- Vehicle Information: 1994 Flarside, XLT, 351w E4OD
SD48b, Quarter Horse, Burn2
Re: SFR+100 and R+100 8065 memory access
Here is proof it is an EEC-IV 8061:
-
- Posts: 274
- Joined: 2021 Feb 16, 15:46
- Location: Australia
- Vehicle Information: 95 Escort RS Cosworth
2.0 YBP
CARD / QUIK / COSY / ANTI
GHAJ0
SMD-190 / SMD-490 EEC-IV
Binary Editor
ForDiag
Re: SFR+100 and R+100 8065 memory access
Yes, now you see it.
STB put 0x0064 at address R13A.
R3a,R3b Endian unadjusted has 0x3a,0x3b.
Endian adjusted the value is 0x3b3a.
No word R3b.
-
- Posts: 274
- Joined: 2021 Feb 16, 15:46
- Location: Australia
- Vehicle Information: 95 Escort RS Cosworth
2.0 YBP
CARD / QUIK / COSY / ANTI
GHAJ0
SMD-190 / SMD-490 EEC-IV
Binary Editor
ForDiag
Re: SFR+100 and R+100 8065 memory access
No its not proof.
8065's in boxes labelled as eec-iv are like weeds.
Suck the code out of it, it is 8065 code.
Pull the lid off it, it is an 8065 inside with 8065 support chip.
U gonna hafta do betta than google pic search
I don't refer to eec-i/v, I say 8061 or 8065 these days.
-
- Posts: 274
- Joined: 2021 Feb 16, 15:46
- Location: Australia
- Vehicle Information: 95 Escort RS Cosworth
2.0 YBP
CARD / QUIK / COSY / ANTI
GHAJ0
SMD-190 / SMD-490 EEC-IV
Binary Editor
ForDiag
Re: SFR+100 and R+100 8065 memory access
Run the test bins, no need to assume.
No, it is 8065.
P3M hardware is 8065 and the test result show that sf/r+100 did not work on that hardware.
VILE hardware is 8065 and the test result show that sf/r+100 did work on that hardware.
-
- Posts: 320
- Joined: 2021 Feb 16, 15:53
- Location: Victoria, BC, Canada
- Vehicle Information: 1994 Flarside, XLT, 351w E4OD
SD48b, Quarter Horse, Burn2
Re: SFR+100 and R+100 8065 memory access
'P3M' (8065, single bank)
Ok, so, the answer is going to be any single bank uP does not support SFR+100 or R+100, where as multi banks do support.
Ok, so, the answer is going to be any single bank uP does not support SFR+100 or R+100, where as multi banks do support.
-
- Posts: 320
- Joined: 2021 Feb 16, 15:53
- Location: Victoria, BC, Canada
- Vehicle Information: 1994 Flarside, XLT, 351w E4OD
SD48b, Quarter Horse, Burn2
Re: SFR+100 and R+100 8065 memory access
Both RAM and ROM.
The P3M.bin is a single bank, and your hardware box does not support bank addressing.
Without having the hardware in hand, I would have to assume that the circuit board does not have the addressing chip that supports bank addressing or it simply does not have the external memory that supports multi bank.
Can you identify which memory chips that are on your hardware?
-
- Posts: 274
- Joined: 2021 Feb 16, 15:46
- Location: Australia
- Vehicle Information: 95 Escort RS Cosworth
2.0 YBP
CARD / QUIK / COSY / ANTI
GHAJ0
SMD-190 / SMD-490 EEC-IV
Binary Editor
ForDiag
Re: SFR+100 and R+100 8065 memory access
0x0 to 0x3ff resides within the uP, not external circuits.
Sf/r+100 is happening inside the uP, not external circuits.
You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.
It is premature to boldly claim that single ROMBANK do not support sf/r+100.
-
- Posts: 320
- Joined: 2021 Feb 16, 15:53
- Location: Victoria, BC, Canada
- Vehicle Information: 1994 Flarside, XLT, 351w E4OD
SD48b, Quarter Horse, Burn2
Re: SFR+100 and R+100 8065 memory access
Correct, memory mapped for speed. SFR 0x00->0x23, Gen. Reg. 0x24->0x3ff for the 8065.
0x0400->0xffff ~57k, one bank is ~64k
Oh boy, here we go with this +100 business. There is no +100 inside the uP, thats a human thing.Sf/r+100 is happening inside the uP, not external circuits.
Inside the uP there is an algorithm that selects which bank pair, either odd or even, using PSW bits and address bits.
Noted.You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.
Non-memory expansion mode set in software only? What is the voltage on PIN-27 of the CPU? (+5v or gnd)
I'm sure the uP are the same, its the circuit board and components are different.
I noted the P3M.bin is a single bank, and "your hardware box does not support bank addressing."It is premature to boldly claim that single ROMBANK do not support sf/r+100.
I claim "Single 64k memory bank hardware will not support sf/r+100, plain and simple, whether it be a 8061 or an 8065".
Hardware being the circuit board, peripherals, etc. not the uP.
Or one could say; "It Depends", the 8065 can be configured to support it, and it can also be configured to not support it.