SFR+100 and R+100 8065 memory access

[wwhite]

The log files in the linked zip show that VILE supports +100 but P3M does not. Both are 8065's but different steppings. It is not random.

Maybe one uP has memory expansion enabled, and the other does not?

[wwhite]

I notice you are logging the PSW, but only bits 0-7, the logical flag bits.

You should also log the following of PSW:
bits 8,9 = RAM bank select bits (RB0, RB1)
bits 10,11,12,13 = ROM bank select bits (MB0, MB1, MB2, MB3)

Log bit 4 of SFR 'a', that is the memory expansion enable.
Read bit 4 of Ra on each uP.
My guess is that Ra bit 4 will be enabled(1) in VILE, and Ra bit 4 will be disabled(0) in P3M.

[jsa]

This is also pseudo code from my head, you get the idea.

Code: Select all

a0, 56, 58    ldw R56, R58    R58 = R56   // EVEN addressing = Bank0, A0=0

Code: Select all

a0, 57, 58    ldw R156, R58    R58 = R156 // ODD addressing = Bank1, A0=1

It is bit position 0 of operand 1 that determines address mode.
The opcode A0 does not equal a different value.

I am 100% positive SAD is not taking account for ^A0 being odd or even to select the correct bank pair for word direct addressing.
.....

I am 100% certain you did not read the first post.
viewtopic.php?p=936#p936

PYM, TVRFan and I aware that the disassemblers are not handling SFR+100 and R+100 memory offsets in all cases.

A lot of SAD is cryptic to me, and I have not been able to get the debugger working.
...
Not sure if the above is a ternary operator, or if the programmer is questioning what is going on. There is no code below this comment.
....
What does PSTPD stand for?

All questions for TVRfan in another thread.
You are welcome to start your own thread for any SAD bugs.

Code: Select all

2344: c7,01,3a,01,3c      stb   R3c,[R0+13a]     Odd_Md_Rg = Odd_Md_Val;

Destination Register R3c in Bank0 will contain the value from Register R3a in Bank1.

No.
This is Store bYte, the opposite order to Load bYte.
Destination Register R13a will contain the value from source register R3c

So, as you can see, the only Data Banks being used are 0 and 2, with the original 3b3a and 64 word values.

Reg R30, with ODD addressing loads values from Bank1 and Bank3, which have not been initialized.

I really do not see, or understand how your test cases are valid.

No, it is not data banks 0 and 2.
No, R30 does not load values from Bank3.

You have contradicted yourself a few times and have STW back to front.

The test code matches code in OEM bins.
The purpose of the test is to see which versions of 8065 support the memory addressing mode added to 8065 at some point.
The test is valid.

I think you should initialize all variables in all banks, and log PSW as well, then look at the results.

Please post your test bin and support files, doing as you believe it should work.

The log files in the linked zip show that VILE supports +100 but P3M does not. Both are 8065's but different steppings. It is not random.

Maybe one uP has memory expansion enabled, and the other does not?

Neither VILE or P3M have memory expansion enabled for the test.

I notice you are logging the PSW, but only bits 0-7, the logical flag bits.

You should also log the following of PSW:
bits 8,9 = RAM bank select bits (RB0, RB1)
bits 10,11,12,13 = ROM bank select bits (MB0, MB1, MB2, MB3)

Log bit 4 of SFR 'a', that is the memory expansion enable.
Read bit 4 of Ra on each uP.
My guess is that Ra bit 4 will be enabled(1) in VILE, and Ra bit 4 will be disabled(0) in P3M.

Neither VILE or P3M are in memory expansion mode for the test.

JFA7 / KMAK6 has none of what?

My disassembly of stock JFA7.bin has no references for ^A0 ldw direct address mode with a SF/R+100.

I think you'll find it has hundreds of SF/R+100
Exhibit A;

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0229d: a0,03,4c           ldw   R4c,R102         R4c = R102;

KRAF5 has hundreds of what?

Hundreds of ^A0 ldw direct address mode with hundreds of SF/R+100 & SF/R+200.

No, not +200.

[wwhite]

PYM, TVRFan and I aware that the disassemblers are not handling SFR+100 and R+100 memory offsets in all cases.

The disassemblers are not handling SF/R+100 memory offset.

I think you'll find it has hundreds of SF/R+100
Exhibit A;

Code: Select all

0229d: a0,03,4c           ldw   R4c,R102         R4c = R102;

Nope I do not see them.
Here is my disassembly of line 229d,

Exhibit Aa;

Code: Select all

0 229d: a0,03,4c             ldw   R4c,R03            R4c = LIO_PORT;  

Which disassembled code is correct?
Maybe they are both incorrect.

[jsa]

If you disagree the tests show R102 as being correct, how are you going to prove what is correct??

[wwhite]

This is also pseudo code from my head, you get the idea.

Code: Select all

a0, 56, 58    ldw R56, R58    R58 = R56   // EVEN addressing = Bank0, A0=0

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a0, 57, 58    ldw R156, R58    R58 = R156 // ODD addressing = Bank1, A0=1

It is bit position 0 of operand 1 that determines address mode.
The opcode A0 does not equal a different value.

Yes correct, but you misread what I typed: opcode a0 != address bit A0.
lower case 'a0' is opcode
uppercase 'A0' address bit 0.

Yes, bit 0 of operand a0 determines address mode Direct.
- bit 0 of address A0 determines ram bank select.

Register 57, address bit 0 is 1, which is odd addressing, which could be register R156, or R356, depends on PSW bit9.

[wwhite]

If you disagree the tests show R102 as being correct, how are you going to prove what is correct??

Using SFR 0x0003, can be accessed as either a byte or a word, and the uP does not use lsb A0, so word register is accessed as R02, always.
General Register 0x004c word will contain hibyte[R02], and 0x004d will contain lobyte[R03].

Back to your test code: a0,3b,30 ldw R30,R13a Log_Rg = Odd_Md_Rg;
Two possible results:
- 1) R30 could contain R13a=0x0064 (d100)
- 2) R30 could contain R3b=0x3b3a. (d15162)

[wwhite]

I am assuming it is the following test results d100 and d15162 that show up on different uPs.

Simple with your test cases, P3M is a 8061, and does not have support for RAM or ROM banks, hence the term single bank.
VILE is a 8065 and has support for RAM and ROM banks.

P3M will result with d15162.
VILE will result with d100.

On some 8065 stepping processors, your concern from above, 3b is actually word 13a.

With P3M being 8061 and VILE being 8065, you have not proved that this does not work on a 8065.

[jsa]

No, P3M is not 8061, it is 8065.

[wwhite]

No, P3M is not 8061, it is 8065.

Prove it.