EFIDynoTuning Forum

Set the Scalar STACK_SFR to 8061 and write the update to the QH.
That will change the Stack SFR from 0x20 to 0x10.
Reboot the EEC, the stack address will be loaded to 0x10.

The OEM stack address does not have to be followed. The stack can be put elsewhere.

Look at the definition spreadsheet. It tells you what is written where for the 8061 and 8065 options.
Look at that address in the LST.
R20 becomes R10 when when STACK_SFR is changed to 8061 then written.
Reboot to take effect.
Both have the stack below 0x200. What catchcode is your BIN?

Both disassemblers will need updates as a result of some test bin results.

viewtopic.php?f=40&t=132

PYM, TVRFan and I aware that the disassemblers are not handling SFR+100 and R+100 memory offsets in all cases.

I have written test bins to dis/prove conjecture around the SF/R+100 memory offset.
The files can be found at;
https://github.com/OpenEEC-Project/EEC- ... -Test-Bins

They are well worth a look.

We'd be interested in your results if you decide to run them on your own hardware.

Edit: Fix link

It is the last source because all subsequent releases in the development branch are beta. Stuff changes a lot in those. 14 is in the melting pot at the moment. If it is a good'n it might make it to full release status, as a messy overhall is after that.

I doubt he even has 13 anymore, it would be well on the way to 14.

His email address is on github last I looked. Ask and he may make 13 ish or 14 when available.

Far as I know major releases will have source available on github.

Shame, ironmans read only idea is agood one

Dead links from google search.

Downloaded a while back from who knows where.

Thank you.

Interesting, does it have some sort of config file per processor type that can be shared?

Both.
The very latest TVRFAN SAD is treating SFR +100 as ford documented.

Pym's SADx treats SFR and general reg as +100


https://github.com/tvrfan/EEC-IV-disass ... evelopment

https://github.com/OpenEEC-Project/SAD806x