EFIDynoTuning Forum

Yes the channels can be added to code.

If uP pins are connected to J1 pins then it is easy.
Otherwise input circuitry needs to configured like voltage in channels.

4.07.16 is the most recent.

Give 1.4 a go.

P3M is an 8065.

Which SAD version?

wwhite wrote: ↑2021 Apr 16, 04:24

You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.

Noted.
Non-memory expansion mode set in software only? What is the voltage on PIN-27 of the CPU? (+5v or gnd)
I'm sure the uP are the same, its the circuit board and components are different.

Pin 27 does not matter to memory, it is for I/O expansion. Input and Output...Sensors and Actuators.

wwhite wrote: ↑2021 Apr 16, 04:24 I claim "Single 64k memory bank hardware will not support sf/r+100, plain and simple, whether it be a 8061 or an 8065".
Hardware being the circuit board, peripherals, etc. not the uP.
Or one could say; "It Depends", the 8065 can be configured to support it, and it can also be configured to not support it.

The relevance, to +100 addressing, of hardware external to the uP has not been established.

wwhite wrote: ↑2021 Apr 16, 12:07 This has been a fun distraction from every day life.
For me, I have learned a lot more about differences with 8061 and 8065, specifically with how the uP decodes how to select different banks.

Once this covid stuff is settled, I would like to buy you jsa, a beer, or a pop whatever you prefer(seriously)!.

Cool. I'm on an island in the south pacific, drop by some time.

wwhite wrote: ↑2021 Apr 16, 12:07SFRs do not use +100, only general registers if there are more than one 64k byte memory chips on board and some other circuit details.

Look at the results for the second test bin. Address x102 to x123 can be accessed using word operations on odd SFR addresses.

Testing one off single ROM bank uP is not enough to be certain of every single ROM back hardware config. They still have R0 to R3FF onboard the uP.

wwhite wrote: ↑2021 Apr 16, 12:07The hardware does what we expect.

I disagree.

wwhite wrote: ↑2021 Apr 16, 12:07Its the disassembly process that is incorrect.

Agree it is a work in progress.

wwhite wrote: ↑2021 Apr 16, 12:07 The disassembly does not know how many fixed hardware 64k memory banks exists in box.

Disagree, printout at the top of the LST file says how many ROM banks are found.

wwhite wrote: ↑2021 Apr 15, 23:01 Both RAM and ROM...

0x0 to 0x3ff resides within the uP, not external circuits.

Sf/r+100 is happening inside the uP, not external circuits.

You should note the test bins are single ROMBANK, and operating in non memory expansion mode. Sf/r+100 still functions on one piece of test hardware.

It is premature to boldly claim that single ROMBANK do not support sf/r+100.

wwhite wrote: ↑2021 Apr 15, 19:19 'P3M' (8065, single bank)

Ok, so, the answer is going to be any single bank uP does not support SFR+100 or R+100, where as multi banks do support.

Which particular memory bank type are you talking about?

wwhite wrote: ↑2021 Apr 15, 18:13

jsa wrote: ↑2021 Apr 15, 18:09 No, P3M is not 8061, it is 8065.

Prove it.

Did you see the stack setting in the test bins...

Try running those test bins.

wwhite wrote: ↑2021 Apr 15, 17:42 I am assuming it is the following test results d100 and d15162 that show up on different uPs.

Run the test bins, no need to assume.

wwhite wrote: ↑2021 Apr 15, 17:42 Simple with your test cases, P3M is a 8061,

No, it is 8065.

wwhite wrote: ↑2021 Apr 15, 17:42 With P3M being 8061 and VILE being 8065, you have not proved that this does not work on a 8065.

P3M hardware is 8065 and the test result show that sf/r+100 did not work on that hardware.

VILE hardware is 8065 and the test result show that sf/r+100 did work on that hardware.