EFIDynoTuning Forum

dleach1407 wrote: ↑2023 Apr 14, 17:06

034v wrote: ↑2023 Apr 13, 16:49 If you have the burn2/fe/fa yes.

Wont work with a Jaybird?

Could not get it to write on the card edge.

Delete it.

If you have the burn2/fe/fa yes.

TI Performance and SCT 6600 only for me.

Update:

All 56k, 64k, 88k 128k, must be a 256k; and tuning residing on bank 8.

0189 standard..

Completely NOT the case with sct or moates f3v2 as all 56k are 032000 03FFFF / 000000 00DFFF

Burn2 with J3 reader and ribbon cable works with burning and reading the chip as a 256k file.

decipha wrote: ↑2023 Mar 30, 23:55 photos are useless no one cares about reading the chip that's completely irrelevant

yea but, look at the picture as the UI is not F&B, nor does it work with the TIP burner.

I can get the chip to read via Burn2/Chip Adapter/Ribbon Cable combo in F&B, but not write. And... not on the J3 card edge at all.

My point is; the TIP burner must pad the 56k 0x0000 to 0x2000 which is bonkers. When I read the chip in F&B and use the normal 56k offsets, its stacked jumbled up. If I read with a 0x0000 to 0xFFFF chip addressing and 0x0000 to 0x0DFFF buffer it gets a clean read. Using that BIN in the TIP burn process with either offset yields a FAIL mode when on the J3. Because again, you have to write with the TIP burner.

Just odd.. wanted to see if anyone else has this issue. 256k, ZERO issues. 56k, pissing me off.

decipha wrote: ↑2023 Mar 30, 07:51 you can't use hardware >> utilities to write it like a jaybird?

No

decipha wrote: ↑2023 Mar 29, 20:06 xdf offset is irrelevant since you dont use nor need an xdf to write

That's my concern.

The Ostrich I/O version 10.10 is what the TIP chip burner uses in TPRT. I can only address offsets when dumping ROM to a file.

When using the upload tune feature, it writes however, when placed on the j3 fuel pump runs constantly.

Only on EEC-IV.

Exactly what I do. Offset in xdf is -2000 (8192 byte), size is E000.

Keep getting Failures even after programing.

Is there a specific buffer or offset to use on the TI chip in a single bank US EEC-IV?

Like 032000 and 03FFFF / 000000 and 00DFFF like normal E000 -2000 XDF's? Or is there a certain secret I'm obviously missing?

Thanks