Search found 437 matches

by jsa
2025 Feb 15, 22:07
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 691
Views: 393521

Re: EEC V file conversion

I reckon the cmpb 34,f2 is looking to see if opcode F2 PUSHP, typical start of a sub, is at 1f1c, and if true call it.
by jsa
2025 Feb 14, 20:47
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 691
Views: 393521

Re: EEC V file conversion

BOOSTEDEVERYTHING wrote: 2025 Feb 14, 13:42 81F1C ...is not a valid address?

Code: Select all

8f7dc: ef,3d,27           call  81f1c            81f1c (); } } }
Search the three manuals for console and look at the allocation of RAM addresses in those and the handbook.

1F1C is a console address. Once a connected console is confirmed, code in the console address space is executed.

Insufficient information in your post to determine anything else.

It gets 'interesting' in FM20M06, which is an unusual multi bank strategy.

Code: Select all

83530: b3,01,1c,1f,34     ldb   R34,[R0+1f1c]    R34 = [11f1c];
83535: 99,f2,34           cmpb  R34,f2           
83538: d7,03              jne   8353d            if (R34 = f2)  {
8353a: ef,df,e9           call  81f1c            81f1c (); } } }
by jsa
2025 Feb 12, 16:08
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 691
Views: 393521

Re: EEC V file conversion

It is bug/mod 28 or 29 of 30. I haven't sent the latest bug list update to TVRfan yet.

EQE3/READ0 has a lot of compares to 7fff which seems to trigger table recognition for 17fff for some strange reason. Many other bins don't trigger it.
by jsa
2025 Feb 05, 20:18
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 691
Views: 393521

Re: EEC V file conversion

Thank you TVRfan for the ever improving SAD.

The attached zip contains updates, intended for SAD4.13.10, to RZASA DIR and CMT previously posted in this thread.
It takes advantage of the naming improvements, pushes SAD a little harder and fixes some DIR/CMT errors.
It includes;
* Updates to Commands, SFR's, SUB's and SYM's
* :F options enabled which is good for flags but not summed bits so beware of the errors.
* Disable some false DMR flags, replacing with temp flags over a range.
* Inline immediate address mode scalars have been enabled with CMT entries to show in LST.
* As examples, a couple FN's have been changed to V4.13.10 math options.
RZASA DIR CMT Upd for SAD4-13-10.zip
(348.46 KiB) Downloaded 115 times
by jsa
2025 Jan 31, 06:19
Forum: Moates Support
Topic: MOATES -- FYI
Replies: 95
Views: 104042

Re: MOATES -- FYI

Welcome back, what's the game plan for the future?
by jsa
2025 Jan 17, 14:32
Forum: A1C - 80/90s EFI-SD4x Speed Density
Topic: A1C XDF Additions
Replies: 61
Views: 53475

Re: A1C XDF Additions

Certainly, change to suit.
Command / Base Register / Base Address / Range Start / Range End

Code: Select all

RBA E2 B494 423D ????
RBA E2 B480 6940 7555
RBA E2 BD55 878B ????
by jsa
2025 Jan 17, 08:11
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 691
Views: 393521

Re: EEC V file conversion

Thank you TVRfan for combining the best of 4.07.16 & 4.12 plus extras into 4.13.7 over the last month or so, and all the bug fixes this week, to make this the most usable SAD for nearly all bins. It is very much appreciated.
by jsa
2025 Jan 16, 20:34
Forum: A1C - 80/90s EFI-SD4x Speed Density
Topic: A1C XDF Additions
Replies: 61
Views: 53475

Re: A1C XDF Additions

efloth wrote: 2025 Jan 16, 15:52 Any idea what address [Re2+ff5d] is referencing? I calculated it using wrap around but landed in code or outside the used program memory.

Code: Select all

6940: 45,d2,00,fc,e2      ad3w  Re2,Rfc,d2       Re2 = b480;
......
7551: b3,e3,5d,ff,3a      ldb   R3a,[Re2+ff5d]   R3a = [Re2+ff5d];
Why not put an rbase command in the SAD DIR and let it do the math?

Code: Select all

RBA E2 B480
by jsa
2024 Dec 25, 00:17
Forum: The Range
Topic: Merry Christmas 24
Replies: 7
Views: 3399

Re: Merry Christmas 24

Merry Christmas and happy New Year to all.