Search found 424 matches

by jsa
2025 Feb 05, 20:18
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 657
Views: 272752

Re: EEC V file conversion

Thank you TVRfan for the ever improving SAD.

The attached zip contains updates, intended for SAD4.13.10, to RZASA DIR and CMT previously posted in this thread.
It takes advantage of the naming improvements, pushes SAD a little harder and fixes some DIR/CMT errors.
It includes;
* Updates to Commands, SFR's, SUB's and SYM's
* :F options enabled which is good for flags but not summed bits so beware of the errors.
* Disable some false DMR flags, replacing with temp flags over a range.
* Inline immediate address mode scalars have been enabled with CMT entries to show in LST.
* As examples, a couple FN's have been changed to V4.13.10 math options.
RZASA DIR CMT Upd for SAD4-13-10.zip
(348.46 KiB) Downloaded 3 times
by jsa
2025 Jan 31, 06:19
Forum: Moates Support
Topic: MOATES -- FYI
Replies: 95
Views: 68323

Re: MOATES -- FYI

Welcome back, what's the game plan for the future?
by jsa
2025 Jan 17, 14:32
Forum: A1C - 80/90s EFI-SD4x Speed Density
Topic: A1C XDF Additions
Replies: 55
Views: 24517

Re: A1C XDF Additions

Certainly, change to suit.
Command / Base Register / Base Address / Range Start / Range End

Code: Select all

RBA E2 B494 423D ????
RBA E2 B480 6940 7555
RBA E2 BD55 878B ????
by jsa
2025 Jan 17, 08:11
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 657
Views: 272752

Re: EEC V file conversion

Thank you TVRfan for combining the best of 4.07.16 & 4.12 plus extras into 4.13.7 over the last month or so, and all the bug fixes this week, to make this the most usable SAD for nearly all bins. It is very much appreciated.
by jsa
2025 Jan 16, 20:34
Forum: A1C - 80/90s EFI-SD4x Speed Density
Topic: A1C XDF Additions
Replies: 55
Views: 24517

Re: A1C XDF Additions

efloth wrote: 2025 Jan 16, 15:52 Any idea what address [Re2+ff5d] is referencing? I calculated it using wrap around but landed in code or outside the used program memory.

Code: Select all

6940: 45,d2,00,fc,e2      ad3w  Re2,Rfc,d2       Re2 = b480;
......
7551: b3,e3,5d,ff,3a      ldb   R3a,[Re2+ff5d]   R3a = [Re2+ff5d];
Why not put an rbase command in the SAD DIR and let it do the math?

Code: Select all

RBA E2 B480
by jsa
2024 Dec 25, 00:17
Forum: The Range
Topic: Merry Christmas 24
Replies: 7
Views: 930

Re: Merry Christmas 24

Merry Christmas and happy New Year to all.
by jsa
2024 Dec 14, 16:46
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 657
Views: 272752

Re: EEC V file conversion

wwhite wrote: 2024 Dec 14, 12:09 Reading the STB - Store Byte opcode description, there is absolutely zero mention of 'WORD'.
Indeed, the expectation being that address modes are well understood.

For STB I said;
R28 holds a word length address, so bytes 1 & 3 are combined as the word length address destination, with a store size of one byte, for the byte length data held in source R2B.
Byte1/R29 is the address word high byte.
Byte3/R28 is the address word low byte.

For STW I'd say;
R28 holds a word length address, so bytes 1 & 3 are combined as the word length address destination, with a store size of one word, for the word length data held in source R2A as an example.
Byte1/R29 is the address word high byte.
Byte3/R28 is the address word low byte.

Software_manual wrote: 3-2.3.5 INDIRECT ADDRESS MODE
.
.
location between addresses ^0000 to '^FFFF using a 16-bit effective address(EA). The 16-bit effective address is
stored as a WORD variable
.
.
by jsa
2024 Dec 13, 14:45
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 657
Views: 272752

Re: EEC V file conversion

wwhite wrote: 2024 Dec 12, 14:25

Code: Select all

8 21be: c6,28,2b             stb   [R28],R2b          [R28] = R2b;         
wwhite wrote: 2024 Dec 13, 12:30
byte 1 and byte 3 are completely unrelated, they shouldn't be combined.
C6 is Indirect address mode.
Software_Manual wrote: 3-2.3.5 INDIRECT ADDRESS MODE
The indirect address mode enables software to access any"A"operand byte or word location between
addresses'^0000 to '^FFFF using a 16-bit effective address(EA). The 16-bit effective address is
stored as a word variable on-board the microprocessor 10 chip. Software specifies the location of
the word variable as an 8-bit address in the R^ component of the address mode format. The word
variable must be address-aligned at its memory location. Indirect addressing is specified at the
assembly source level by any operand label or address prefixed with the symbol, e.g., ADCB
@TEMP,SCALE or ADCB @'^2A,'^B6 where TEMP and ^2A are "A"operand designators.
R28 holds a word length address, so bytes 1 & 3 are combined as the word length address destination, with a store size of one byte, for the byte length data held in source R2B.
Byte1/R29 is the address word high byte.
Byte3/R28 is the address word low byte.
by jsa
2024 Dec 13, 06:48
Forum: Hardware, Programming & Disassembly
Topic: EEC V file conversion
Replies: 657
Views: 272752

Re: EEC V file conversion

wwhite wrote: 2024 Dec 12, 14:25

Code: Select all

8 21a9: a1,c8,89,26          ldw   R26,89c8           R26 = 89c8;      
8 21ad: b2,27,29             ldb   R29,[R26++]        R29 = [R26++];       <-----Byte 1

8 21b8: b2,27,28             ldb   R28,[R26++]        R28 = [R26++];       <-----Byte 3
The 8061's I've looked at have been a simple offset for which STRuct has an option.

If you've found a way to use the struct command to combine byte 1 & 3 and give a usable result please post the command and options from your DIR?

Thanks for the AI attempt. Confirms my earlier statements.